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Thursday, August 15, 2019

Reference-Page-For: Yosys is a framework for Verilog RTL synthesis


Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Selected features and typical applications:
  • Process almost any synthesizable Verilog-2005 design
  • Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
  • Built-in formal methods for checking properties and equivalence
  • Mapping to ASIC standard cell libraries (in Liberty File Format)
  • Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
  • Foundation and/or front-end for custom flows
Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the Yosys C++ code base.
Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license).

Example Usage

Yosys is controlled using synthesis scripts. For example, the following Yosys synthesis script reads a design (with the top module mytop) from the verilog file mydesign.v, synthesizes it to a gate-level netlist using the cell library in the Liberty file mycells.lib and writes the synthesized results as Verilog netlist to synth.v:
# read design 
read_verilog mydesign.v

# elaborate design hierarchy
hierarchy -check -top mytop

# the high-level stuff
proc; opt; fsm; opt; memory; opt

# mapping to internal cell library
techmap; opt

# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib

# mapping logic to mycells.lib
abc -liberty mycells.lib

# cleanup

# write synthesized design
write_verilog synth.v
The synth command provides a good default script that can be used as basis for simple synthesis scripts:
# read design 
read_verilog mydesign.v

# generic synthesis
synth -top mytop

# mapping to mycells.lib
dfflibmap -liberty mycells.lib
abc -liberty mycells.lib

# write synthesized design
write_verilog synth.v
See help synth for details on the synth command.



All other links below-this-line are to other projects.

Online Services

  • EDA Playground -- Web Interface to many EDA tools, including Yosys
  • Blinklight -- A visual FPGA dev tool for simple designs

Free Verilog Simulators

Free Software for High-Level Circuit Synthesis and/or Analysis

  • Chisel -- Constructing Hardware in a Scala Embedded Language
  • PandA -- high-level synthesis of C based descriptions
  • CLaSH -- A compiler from Haskell to Verilog/VHDL
  • MyHDL -- an open source Python package that lets you go from Python to silicon
  • Migen -- a Python-based tool that aims at automating further the VLSI design process
  • Cx -- A modern C-like language to create digital hardware

Free Software for Low-Level Circuit Synthesis and/or Analysis

  • ABC -- extensive tools for synthesis and verification of binary sequential logic
  • AIGER -- a format, library and set of utilities for And-Inverter Graphs
  • MiniSAT -- the SAT solver library used in Yosys
  • Torc -- infrastructure and tool set for mapping, placing, and routing
  • RapidSmith -- a research-based, open source FPGA CAD tool for modern Xilinx FPGAs
  • Open Circuit Design -- collection of open-source EDA tools, including Qflow
  • Coriolis2 -- an ASIC place and route flow
  • Workcraft -- a framework for interpreted graph models
  • netlistsvg -- SVG schematic from a Yosys JSON netlist

Verilog Tutorials


This page has links to all the documentation resources available for Yosys.

Yosys Manual

A quick first-steps tutorial can be found in the README file.
The Yosys manual can be downloaded here (PDF).


The best places to ask questions are the Yosys Subreddit, Stack Overflow and #yosys on freenode. The best place to report a bug is on GitHub.

Presentation Slides

This presentation slides cover a wide range of topics related to Yosys. (The LaTeX source is part of the Yosys source distribution. Fell free to adapt the slides as needed.)

Application Notes

Papers and other Publications

This section is under construction.

In papers and reports, please refer to Yosys as follows: Clifford Wolf. Yosys Open SYnthesis Suite., e.g. using the following BibTeX code:
 author = {Clifford Wolf},
 title = {Yosys Open SYnthesis Suite},
 howpublished = "\url{}"

Command Reference

Yosys HQ / Yosys Open SYnthesis Suite