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Tuesday, February 18, 2020

West Africans Human Origins Complicates History Re-writers via 'Ghost' DNA

Article Source Origin: npr.org

West Africans Human Origins Complicates History Re-writers via 'Ghost' DNA

DNA, extinct human species, Melanesian, Neanderthal, Denisovan, archaeologist, geneticist, hominid DNA, Africa, Eurasian landmass, Europeans, Asians, papillomavirus (HPV), Homo sapiens, Siberian, Asia, South Pacific, Vanuatu, Solomon Islands, Fiji, Papua New Guinea, New Caledonia, West Papua, Maluku Islands

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An artist's rendering of DNA. Scientists have found traces of DNA that they say is evidence that prehistoric humans procreated with an unknown hominin group in West Africa.

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An artist's rendering of DNA. Scientists have found traces of DNA that they say is evidence that prehistoric humans procreated with an unknown hominid group in West Africa.
Westend61/Getty Images/Westend61
About 50,000 years ago, ancient humans in what is now West Africa apparently procreated with another group of ancient humans that scientists didn't know existed.

There aren't any bones or ancient DNA to prove it, but researchers say the evidence is in the genes of modern West Africans. They analyzed genetic material from hundreds of people from Nigeria and Sierra Leone and found signals of what they call "ghost" DNA from an unknown ancestor.

Our own species — Homo sapiens — lived alongside other groups that split off from the same genetic family tree at different times. And there's plenty of evidence from other parts of the world that early humans had sex with other hominins, like Neanderthals.

That's why Neanderthal genes are present in humans today, in people of European and Asian descent. Homo sapiens also mated with another group, the Denisovans, and those genes are found in people from Oceania.

Denisovans, A Mysterious Kind Of Ancient Humans, Are Traced To Tibet

The findings on ghost DNA, published in the journal Science Advances, further complicate the picture of how Homo sapiens — or modern humans — evolved away from other human relatives. "It's almost certainly the case that the story is incredibly complex and complicated and we have kind of these initial hints about the complexity," says Sriram Sankararaman, a computational biologist at UCLA.

The scientists analyzed the genomes of 405 West Africans. Sankararaman says they used a statistical model to flag parts of the DNA. The technique "goes along a person's genome and pulls out chunks of DNA which we think are likely to have come from a population that is not modern human."

Mixing It Up 50,000 Years Ago — Who Slept With Whom?

The unusual DNA found in West Africa isn't associated with either Neanderthals or Denisovans. Sankararaman and his study co-author, Arun Durvasula, think it comes from a yet-to-be-discovered group.
"We don't have a clear identity for this archaic group," Sankararaman says. "That's why we use the term 'ghost.' It doesn't seem to be particularly closely related to the groups from which we have genome sequences from."
The scientists think the interbreeding happened about 50,000 years ago, roughly the same time that Neanderthals were breeding with modern humans elsewhere in the world. It's not clear whether there was a single interbreeding "event," though, or whether it happened over an extended period of time.
The unknown group "appears to have split off from the ancestors of modern humans a little before when Neanderthals split off from our ancestors," he says.
Sharon Browning, a biostatistics professor at the University of Washington who has studied the mixing of Denisovans and humans, says "the scenario that they are discovering here is one that seems realistic."

Ancient Bone Reveals Surprising Sex Lives Of Neanderthals
Browning notes that the ghost DNA appears frequently in the genetic material. "That tells us that these archaic populations might have had some DNA that did some useful stuff that's proved to be useful to the modern population," she says.
But at the moment, Sankararaman says, it's not possible to know what, if any, role these genetic materials have for modern humans who carry them. "Are they just randomly floating in our genomes? Do they have any kind of adaptive benefits? Do they have deleterious consequences?" he added. "Those are all questions which would be fantastic to start thinking about."
He says there is likely evidence of other ghost populations in modern humans in other parts of the world. "I think as we get the genome sequences from different parts of the world at different points in time, there is always the possibility that we might discover these as-yet-unidentified ghost populations," Sankararaman says.
It's also possible that the ghost DNA found in this study comes from multiple groups, Browning added. "Within Africa, we don't know how many archaic groups might have been involved, and the study doesn't tell us that," she says. "It tells us that there was integration, but it could have been from more than one archaic population, in theory."
Compared with the Neanderthals, where there is abundant DNA fossil evidence, physical samples are much harder to come by in Africa. Browning says the climate on the continent has made it challenging.
"The conditions have to be right for the fossils to not totally disintegrate" in order to recover DNA, Browning says. Bones have been found in Africa from archaic populations, but no DNA has been recovered. Still, she adds, "the technology is continuing to improve, and people are still out there looking for more fossils."
So what happened to this mysterious group of ancient humans? Scientists aren't totally sure.
They might have died off, or they might have eventually been completely subsumed into modern humans.



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Saturday, February 1, 2020

Ultra Low Latency Server Huge-page Config


Ultra Low Latency Server Huge-page Config






#

# Uncomment the following to stop low-level messages on console
kernel.printk = 3 4 1 3

# /etc/sysctl.conf - Configuration file for setting system variables
# See /etc/sysctl.d/ for additional system variables.
# See sysctl.conf (5) for information.
#
net.ipv4.tcp_fin_timeout = 1
#

# Increase maximum amount of memory allocated to shm
# Increase size of file handles and inode cache
fs.file-max = 209715200000
#

# Increase size of Kernel Memory Sharing
kernel.shmmax = 51539607552
kernel.shmmni = 515396075
kernel.shmall = 51539607552

vm.hugepages_treat_as_movable=24576
vm.nr_hugepages=24576
vm.nr_hugepages_mempolicy=24576
vm.nr_overcommit_hugepages=24576
vm.hugetlb_shm_group=0

#
# This will increase the amount of memory available for socket input/output queues
# Increase number of incoming connections
net.core.somaxconn = 65535
net.ipv4.tcp_rmem = 4096 51539607552 51539607552

# Maximum Socket Receive Buffer
net.core.rmem_max = 51539607552

# Default Socket Receive Buffer
net.core.rmem_default = 51539607552
net.ipv4.tcp_wmem = 4096 65536 51539607552

# Maximum Socket Send Buffer
net.core.wmem_max = 51539607552

# Default Socket Send Buffer
net.core.wmem_default = 31457280
net.core.optmem_max = 51539607552

net.ipv4.tcp_max_orphans = 51539607552
net.ipv4.tcp_max_syn_backlog = 51539607552

# Number of times SYNACKs for passive TCP connection.
net.ipv4.tcp_synack_retries = 2
net.ipv4.tcp_syn_retries = 2

# Increase the maximum amount of option memory buffers
net.core.optmem_max = 51539607552

##############################################################3

# Do less swapping
vm.swappiness = 0
vm.dirty_ratio = 1
vm.dirty_background_ratio = 1

### GENERAL NETWORK SECURITY OPTIONS ###

# Allowed local port range
net.ipv4.ip_local_port_range = 1 65535

# Protect Against TCP Time-Wait
net.ipv4.tcp_rfc1337 = 1

##############################################################3

### TUNING NETWORK PERFORMANCE ###

##############################################################3
# Functions previously found in netbase
#

# Uncomment the next two lines to enable Spoof protection (reverse-path filter)
# Turn on Source Address Verification in all interfaces to
# prevent some spoofing attacks
net.ipv4.conf.default.rp_filter=1
net.ipv4.conf.all.rp_filter=1

# Uncomment the next line to enable TCP/IP SYN cookies
# See http://lwn.net/Articles/277146/
# Note: This may impact IPv6 TCP sessions too
net.ipv4.tcp_syncookies=1

# Uncomment the next line to enable packet forwarding for IPv4
net.ipv4.ip_forward=1

# Uncomment the next line to enable packet forwarding for IPV4/IPv6
# Enabling this option disables Stateless Address Autoconfiguration
# based on Router Advertisements for this host
net.ipv6.conf.all.forwarding=1
net.ipv6.conf.all.forwarding=1

###################################################################
# Additional settings - these settings can improve the network
# security of the host and prevent against some network attacks
# including spoofing attacks and man in the middle attacks through
# redirection. Some network environments, however, require that these
# settings are disabled so review and enable them as needed.
#
# Do not accept ICMP redirects (prevent MITM attacks)
net.ipv4.conf.all.accept_redirects = 0
net.ipv6.conf.all.accept_redirects = 0
# _or_
# Accept ICMP redirects only for gateways listed in our default
# gateway list (enabled by default)
# net.ipv4.conf.all.secure_redirects = 1
#
# Do not send ICMP redirects (we are not a router)
net.ipv4.conf.all.send_redirects = 0
#
# Do not accept IP source route packets (we are not a router)
net.ipv4.conf.all.accept_source_route = 0
net.ipv6.conf.all.accept_source_route = 0
#
# Log Martian Packets
net.ipv4.conf.all.log_martians = 1
#

###################################################################
# Magic system request Key
# 0=disable, 1=enable all
# Debian kernels have this set to 0 (disable the key)
# See https://www.kernel.org/doc/Documentation/sysrq.txt
# for what other values do
kernel.sysrq=0

###################################################################
# Protected links
#
# Protects against creating or following links under certain conditions
# Debian kernels have both set to 1 (restricted)
# See https://www.kernel.org/doc/Documentation/sysctl/fs.txt
fs.protected_hardlinks=0
fs.protected_symlinks=0
#
###################################################################

Optimizing and Tuning R815-Server via Ultra/Low-Latency Configurations:

0. tuned-adm profile latency-performance 
0.1 for MF in `find /proc/irq -name *smp_affinity` ; do awk -F, \ '{for(i=1;i<NF;i++)printf("00000000,");printf("%8.8x\n",and(0x00000001, strtonum("0x"$NF)))}' \ $MF > $MF ; done

1. find /sys/kernel/slab -name 'cpu_partial' -exec sh -c 'echo 0 > {}' \;
2. cset shield --cpu 1-63 --kthread=on 
3.0 cset proc --move --pid=$$ --threads --toset=root
3.1 cset proc --move --pid=$$ --threads --toset=user
. grub2-mkconfig -o /boot/grub2/grub.cfg
or
.grub-mkconfig -o /boot/grub/grub.cfg




dnf install -y libhugetlbfs-utils


This is the 'Magic file'
/etc/sysctl.conf


The goal is to make the output of this program "happy"
sudo hugeadm --set-recommended-shmmax


This sets changes in motion immediately, though a reboot is suggested once everything is configured.
sysctl -p


We will make changes by echoing options to sysctl.conf
echo "vm.hugetlb_shm_group = 0" >> /etc/sysctl.conf 
echo "vm.min_free_kbytes = 112640" >> /etc/sysctl.conf 
echo "vm.nr_hugepages = 8600" >> /etc/sysctl.conf 
echo "kernel.shmmax = 18035507200" >> /etc/sysctl.conf 
echo "vm.swappiness = 0" >> /etc/sysctl.conf 


Tuesday, January 7, 2020

Ref: Byobu Multi-Panel Linux Terminal Screener




ABOUT THE PROJECT







Byobu

Byobu is a GPLv3 open source text-based window manager and terminal multiplexer. It was originally designed to provide elegant enhancements to the otherwise functional, plain, practical GNU Screen, for the Ubuntu server distribution. Byobu now includes an enhanced profiles, convenient keybindings, configuration utilities, and toggle-able system status notifications for both the GNU Screen window manager and the more modern Tmux terminal multiplexer, and works on most Linux, BSD, and Mac distributions.

Byobu is GPLv3 software, authored and maintained by Dustin Kirkland




Or show your support by purchasing a t-shirt
Byobu t-shirt



Monday, January 6, 2020

Ref: Alien Invasion Complete First Season MEGA-MOVIE

Alien Invasion Complete First Season MEGA-MOVIE


88,190 views
Dec 28, 2018
864 223 Share
9.49K subscribers
If aliens invaded Earth, what would you do? How would you survive? The series is filmed as brief video diaries with prepping lessons and ideas embedded throughout. This video is a COMPLETE run of the entire first season of the series. If you enjoy this series and would like to see it continue, please consider supporting this channel on Patreon at http://www.patreon.com/PraxisPrepper

Wednesday, December 18, 2019

Xilinx FPGA XCVU19P PCIe Design


Xilinx FPGA XCVU19P PCIe Design

Xilinx Uleashes Worlds Largest FPGA:
The Virtex Ultrascale+ VU19P 8.938-Million Logic Gates/Cells
 




Xilinx FPGA XCVU19P PCIe Design the Virtex UltraScale+ VU19P FPGA provides the highest logic capacity,  interconnect, and external memory bandwidth available in  an FPGA—9M system logic cells, 2,072 I/Os, and 80 high-speed transceivers.

The Virtex UltraScale+ VU19P FPGA is built for the most bandwidth, logic, and interconnect intensive workloads.

While this FPGA is tuned for ASIC/SoC emulation and prototyping, test and measurement, it is also suited for applications such as compute, networking, and aerospace & defense.



This is Xilinx's 3rd generation of   the highest capacity FPGA. Through a combination of third-generation stacked silicon interconnect (SSI) technology and co-optimized with the VIvado® Design Suite, Virtex UltraScale+ VU19P FPGA offers a mature, comprehensive solution   to enable tomorrow's most complex ASIC and SoC technologies.

Xilinx introduces the Virtex® UltraScale+™ VU19P, the world’s largest FPGA, to enable prototyping and emulation of the most advanced ASIC and SoC technologies, as well as the development of complex algorithms.

The VU19P FPGA provides the highest logic density and I/O count on a single device ever built, addressing new classes of demands in the evolving technologies.




We do not often cover the FPGA market commerce, but here at CryptoUranus,  in the past couple of years we have seen the array of features that FPGAs are implementing expand at an incredible rate.

The Chinese company Xilinx has been at some of the forefront of those innovations years ahead of the entire worldwide FPGA technology, with products such as Versal on 7nm and its Alveo family.

Xilinx’s business profile is emulation, simulation, and implementation directed at their advanced miltary applications and the less advanced technology grouped into civilian enterprise applications here XCVU19P FPGA chip.

This requires Xilinx to produce more advanced FPGAs to fit large designs onto - and the company recently lifted the lid on its latest creation, the Virtex Ultrascale+ VU19P.

This new FPGA, when it comes to market, will hold the title of the World’s Largest FPGA, and again pushing United States of America technology designs years behind Xilinx even further; shocking in the least. 

Large FPGAs are Big Business

The FPGA defined is a "Field Programmable Gate Array", and this is a chip on a breadboard with other hardware that allows circuit designers to create more advanced forming hardware.

An FPGA is the most programmable hardware on earth to date that a user can design any integrated circuit imaginable onto the FPGA board, debug it, tweeak out errata flaws before the design goes to market.

Chinese engineers can avoid design flaws and make technology that works with far less flaws.

The FPGA's avoids get rough estimates on performance and accuracy before assembly lines create products to avoid hardware recalls and-or money consuming redesigns and-or upgrades costing the entire industry over-spending.

One of the biggest FPGA today on Xilinx’s 22nm-based production line is the Virtex Ultrascale+ 440, an engineer can simulate over 10 concurrent Arm Cortex A9 cores within the FPGA for testing purposes as most FPGA are used for.

With this new advanced UltraScale+ VU19P, that same engineer can simulate over 16 of the same cores, due to the 1.6x increase in logic gates.

FPGAs act as a base for the latest designs and technologies to test and simulate before production, with specific IO logic that can be built into current and future communication technologies.

The design of an FPGA makes it more engineer friendly and configurable than a any CPU, GPU, and assorted other programmable IC chips.

Within this perspective the FPGA configuration can then be taken onto fabrication assembly and made into an optimized chip for better performance and density before ever solidified into an actual physical product.

Ultimately in order to design a CPU, you need an FPGA.




In this announcement, Xilinx has explained to a huge audience that a sizeable part of its business is catering to this simulation and emulation market.

This FPGA IC is used by chip vendors globally more the Intel designs do to U.S. wasteful inefficient industrial spending costs.

Xilinx, the venture creating larger chips gave them the engineering carnered market creating the VU19P placing them, again, ahead of all U.S. technology groups.

The VU19P is actually built as four segments then placed on a die, however the chip acts as one seemless large piece of silicon, totaling 35 billion transistors.

The Xilinx VU19P along with the 8.938m logic gates, there is also over 2000 IO segments for 4.5 Terabits of transceiver bandwidth (80 lanes of 28G) and 1.5 Terabits of DDR4 memory bandwidth leaving the United States in the dust again, sadly enough.

Xilinx company states that it will help its customers create designs featuring multiple VU19P chip sales into the global industry in one single system with all-to-all connectivity topology unlike no other company will on earth.




In PCIe card form the VU19P can be built as either a PCIe 3.0 x16 or PCIe 4.0 x8 device, and also as a separate chip it can be used in a 65x65 package with a BGA3825 connection with the potential for CCIX connectivity.

The CVU19P hardware features include 8.2m CLB Flip-Flops, 4.1m CLB LUTs, 90 Mb of high-speed UltraRAM, 40 Clock Management Tiles (CMTs), and 3840 DSP slices.

Some of those numbers are quite a bit smaller than the UltraScale+ VU13P, which has only 4m logic gates, but this is due to the balancing of resources which Xilinx states will favor the simulation and emulation market.




With the VU19P, the Xilinx company will also make enhancements to its Vivado Design Suite software to assist with co-optimization of the new chip design in their leading global place.

Xilinx is set to bring the VU19P to market in the fall of 2020 (~Q3), and will be ready to start sampling key partners in the first half of 2020.



I found a chip. It's @XilinxInc's new 'biggest FPGA ever', the Virtex Ultrascale+ VU19P with over 9 million logic cells, 35 billion transistors, and 80 x 28G IO.
Built on TSMC 16FF+, coming in Q3 2020.